In System-on-Chip (SoC) designs, the size of embedded memory is typically in the order of megabytes. On processor-based SoC designs, cache and tightly coupled memories are commonplace. The current pace of memory technology has surpassed Moore's Law concerning the density and performance of integrated circuits by greater than a factor of two. Thus, in a typical SoC design, memories command a substantial amount of silicon and/or board real estate and power. Further, the increasing demand for handheld devices, ranging from mobile phones to gaming devices, imposes a critical need for saving power.
Conventional memory technology includes power saving features, such as the so-called “light sleep, “deep sleep”, and shutdown” modes, each of which can be entered in response to providing an appropriate voltage level on a corresponding input of the memory device. For example, when a light sleep (LS) input on the memory device is active, the memory device will enter a low leakage mode, in which output pins on the memory device remain static. Similarly, when a deep sleep (DS) input on the memory device is active, power to the peripheral circuits of the memory device is removed, output pins of the memory device are pulled low, and the contents of the memory device are retained in their current state. Likewise, when a shutdown (SD) input on the memory device is active, contents of the memory device are lost, and power is removed from peripheral circuits of the memory device and its core.
Given the power saving memory features, a logic circuit may be used to drive the power saving input pins (LS, DS, and SD) of the memory device. One solution involves connecting an inverted chip select signal (˜CS) to the LS and DS inputs, and holding the resulting signal inactive for a few additional clock cycles, which results in less activity and power consumption. However, in comparison with the CS setup time, the LS and DS setup times (or more specifically, the LS and DS fall recovery times) are quite large. For example, setup times for a Virage® SRAM (part number V111HDPWV4096M16X36B2L8HS) on a slow—125—0.81 corner (which is a process, voltage, temperature (PVT) corner at which the worst timing delay is exhibited and thus must be considered during design) are shown in Table 1.
TABLE 1Setup TimeSetup time withMemory Specification(nanoseconds)respect to CSCS setup time0.40921x  LS rise setup time0.11880.29xLS fall setup time0.91742.24xDS rise setup time0.35860.88xDS fall setup time3.92269.59x
One solution includes holding the LS input pin low or inactive-if the LS rise setup time specification cannot be met and high or active if the LS fall setup time specification cannot be met. However, this solution eliminates the maximum benefit that we could get out of the light sleep mode. Similarly, if the DS rise setup time specification cannot be met, the DS pin may be tied low or inactive if the DS fall setup time specification cannot be met. However, this solution eliminates the maximum benefit that can be obtained from the deep sleep mode. Thus, logic internal to the memory device used to implement these feature becomes redundant, which results in wasted chip real estate. To achieve optimally power efficient designs, most if not all power saving features should be implemented. Alternatively, memory devices without the unused features should be utilized.
Another solution includes connecting an inverted CS (˜CS) signal to the LS input in such a way that the currently accessed memory bank will be active while the remaining memory devices or bank(s), which are not currently being accessed, enter the light sleep mode. However, in this approach, there may be some latency and/or wait states required when memory banks are switched, such as when a currently dormant (not currently being accessed) memory bank or device is to be accessed. Naturally, if a particular system configuration requires only one memory bank, this approach is inappropriate. A similar result occurs if the processor, to which the memory devices are attached, cannot operate with wait states, such as if cache memory is implemented.